Development of a Scalable FPGA-Based Floating Point Multiplier Summary

This paper presents the implementation of a general purpose, scalable architecture used to synthesize floating point multipliers on FPGAs. Although several implementations of floating point units targeted to FPGAs have been previously reported, most of them are customized for specific applications. This new implementation is different in the sense that it accepts as a user parameter the operand size of the unit about to be synthesized and creates the requested unit. This feature makes our implementation a very convenient tool for rapid application prototyping. An evaluation of several multipliers of different typical sizes synthesized for testing purposes is also presented, highlighting the strengths and limitations of this approach in the creation of custom floating-point units. A comparison between our results and some previously reported implementations shows that our approach, in addition to the scalability feature, provides multipliers with significant improvements in area and speed. Abstract This paper presents a scalable architecture for developing custom floating point multipliers targeted to FPGA